Wireless communication systems, for example cellular or private mobile radio (PMR) communication systems, typically provide for radio communication links to be arranged between a wireless communication network comprising a plurality of base stations (BSs) and a plurality of communication devices, often termed mobile stations (MSs). The MS may be a portable or mobile telephone, a Personal Digital Assistant (PDA), a wireless video or multimedia device, a portable computer, or the like.
A MS typically comprises a RF transceiver block for providing the RF transmit and receive paths of the MS, a baseband block for processing baseband signals received from the RF transceiver block or to be transmitted by the RF transceiver block, and a processing unit for controlling the operation of the MS. The MS further includes a timer, typically known as a layer one timer, which controls the timing and synchronisation of the events and processes in the MS. For example, the layer one timer can assist in synchronising the MS with a BS to ensure that events are processed in a timely manner relative to the radio-air interface. The layer one timer is controlled by a baseband processor which may be part of or separate to the processing unit or may be part of the baseband block. In modern MS devices, typically the RF transceiver block provides an accurate system clock signal which is used as a timing reference for the baseband block, for example as a timing reference for the layer 1 timer. This means that the timing of all events in the MS will be controlled by the system clock signal provided by the RF transceiver block. It is therefore not acceptable to allow this clock reference to accumulate significant error over time. The acceptable level of error is determined by system requirements.
Currently, the most ubiquitous 2nd generation cellular communication system is the Global System for Mobile communication (GSM). In order to enable data to be transferred at much higher data rates than the rates available under GSM, a number of enhancements and additions have been introduced to the GSM communication system. One such enhancement being the General Packet Radio System (GPRS) which uses packet switched data rather than circuit switched data and so makes much more efficient use of the available capacity. Another such enhancement to the GSM communication system is the Enhanced Data rates for GSM Evolution system, which is more commonly known as the EDGE system, a 2.5G system. 3rd generation (3G) systems, such as the Universal Mobile Telecommunication System (UMTS) have been developed and deployed to further enhance the communication services provided to MSs compared to those communication services provided by GSM.
Multi-mode MSs have been developed which are capable of operating in more than one communication system. A WEDGE (WCDMA and EDGE) capable MS, for example, is a dual mode MS which, can operate in a 2G and a 3G system. In a WEDGE dual mode MS, due to the high data rates employed by the 3G protocol, it is increasingly common that the RF transceiver block of the MS employs a 3G DigRF interface standard or similar protocol supporting high data rates to govern its communication with the baseband block. The 3G DigRF standard specifies a 312 Mbps data rate between the RF transceiver block and the baseband block and thus, one consequence of using a 3G DigRF interface is that the RF receiver block requires a high speed Phase Lock Loop (PLL) (for example a 1248 MHz PLL) in order to generate the 312 MHz data clock. The system clock which is used as the timing reference for the baseband block as discussed above may also be derived from this high speed PLL circuit. Observation of the signal received at the RF transceiver block from a BS is used to calibrate the local frequency reference in the PLL circuit through manipulation of the PLL circuit (e.g. by adding a correction to the divider in the PLL circuit) so as to generate a corrected system clock. This ensures that the level of error in the system clock is kept to an acceptable error by means of the PLL circuit. Other techniques are known to correct the errors in the system clock, for example, the tuning voltage to a voltage controlled crystal oscillator (VCXO) can be changed via a Digital-to-Analog Converter (DAC) in order to correct for frequency errors. However, such analog techniques, such as the VCXO and DAC solution, provide less flexibility than a PLL circuit.
However, as the speed of a PLL circuit increases, the current and hence power consumption of the PLL circuit increases. Since in 2G systems, the data transfer rates are normally much lower than in 2.5G and 3G systems, single mode 2G MSs do not need a high speed PLL circuit for the interface between the RF transceiver block and the baseband block. Hence less power is required to generate the system clock in a single mode 2G MS compared to a 3G DigRF enabled dual mode WEDGE MS. Typically, current drain savings of the order to 1-2 mA can be expected in 2G systems compared to 3G systems. Furthermore, in a single mode 2G MS when there are no transmit or receive signals, the MS can enter an idle mode in which the RF transceiver can be almost completely shut down. In such an idle mode with the RF transceiver almost completely shut down, low current is required and hence power consumption is low. However, this is not possible with the current designs of a dual mode WEDGE MS since the high speed PLL must be continually active to ensure accuracy of the system clock by providing a corrected system clock to the baseband block.